Sort of... RISC and CISC are really misnomers. The problem with X86 is not the number of instructions (ARM has a lot too!) but the variable length and difficult to decode instruction format. It's fine to have tons of instructions if they are trivial to decode and decoding can be easily parallelized.
CISC was not a mistake when RAM was hundreds of dollars per kilobyte in the 70's and early 80s. Made sense to get as much out of a byte of memory instruction-wise as possible.
Not exactly a mistake, more of a compounding factor of market forces, who could execute and deliver (and who could not), and the rise of worse is better.
The 80s was a time of research and experimentation, occasionally getting pretty wild. Intel had an «object-oriented» CPU, iAPX 432, which has slightly faster than immediately flopped. And they also had a hybrid RISC/VLIW design (i860) that could be outperform every other design out there – if the stars up in the sky would converge in the right space and time sequence, and the compiler could bundle instructions up efficiently.
Intel also had a very good i960 RISC design. Which was, in fact, so good that the boys with MBA over at Intel have got stumped not knowing what to do with it and chickened out (i960 was considered as a x86 replacement for a time and the future would look quite different from today).
Motorola was flirting with CPU's for a long while as well, but never took them seriously enough to see them through to the end as a serious business, for defence contracts and the field radio equipment (and later mobile phones) were their two major cash cows.
By the way, Motorola also had cool DSP designs with the true Harvard architecture with multiple data buses, and a single 3 operand instruction, e.g. «ADD A, B, C» could transfer A, B, C using three separate data buses – simultaneously. Data transfers were insanely fast.
INMOS got busy building transputers that could be «grown» infinitely (theoretically) into a gigantic computing «thing», and were programmed in Occam, with no assembly language even being available for the chip. They did not get anywhere.
The Japanese built the Smalltalk VM byte codes into a Katana processor, and were mulling over the idea of doing the same for Prolog. Prolog and AI started getting really big back then until both faded into obscurity for a couple of decades.
There was no shortage of great designs and ideas, but no-one had an idea of what the future of personal computing was going to be, therefore everyone was hedging varying bets. Digital had great hardware but they bet on minicomputers and snobbishly continued to ignore PC's until it was too late. They actually missed the server market boat as well as, by the time when they arrived, the bed had already become crowded with new lovers, and only the ones who had more money could win.
RISC vendors were riding the wave out with servers and workstations, until around the mid-aughts, when Intel finally ramped up the production of cheap and dirty Pentium 4 CPU's that could be used in a simple SMP set up, and Google / Facebook were quick to proceed with building out their own server farms filled with cheap and disposable commodity x86 blades. It quickly became too expensive for vertically integrated RISC vendors to keep their own CPU design teams on the payroll. One by one, the RISC vendors have all, too, gradually faded into obscurity.
One thing that absolutely sucked back them was that nearly no one could afford any of those amazing toys, unless it was a business with a fat budget. You could read, but you could not touch most of them. The documentation was gorgeous, though, and also prepared by professional technical writers in Adobe FrameMaker. Now, I can spin up a VM in a public cloud with a custom built TPU (or, NPU) within a few moments, use for as long as I have to, and I won't have to leave my own desk chair and it will be mine for as long as I can afford paying for it.
All of that has left one with pretty much one living CISC fossil and multiple off-shots of the load-and-store architecture, of which RISC is one.
