Ah, but PC Magazine has "9 things you need to know" about it, which includes an incorrect explanation of what a nanometer is. I think it's in a sidebar next to their "38 makeup tips for the summer" article.
Agreed. It's all magic to me but it seems like, if this breakthrough can keep Moore's Law chugging, it's worth a pretty penny. I'm surprised their stock isn't up more today.
Awesome! The current a transistor can put out is porportional to the width over the length and chip designers usually want wide transistors[1], but wide transistors take up space which causes more line capacitance. This innovation will let people put more, wider transistors in a given area which will both increase the current they're putting out and decrease the capacitance they're fighting against, leading to higher frequencies[2].
[1] Wider transistors also cause more capacitance for the other transistors that are driving them, but for most modern designs this is smaller than line capacitance.
[2] Having transistors closer together can also help overcome speed-of-light delay. This can be important in caches.
EDIT: Also, some stuff I didn't notice until reading the Anandtech article is that the thinness of the silicon will give you the same artificial limitation of the depletion region that SOI does, leading to the same accelerated inversion. Oh, and better isolation from the base too. I don't think that I can explain that succinctly for non-EEs so go read Wikipedia on MOSFETs if you're interested.
> Having transistors closer together can also help overcome speed-of-light delay. This can be important in caches.
But in this case, while they take up less space, the distance is the same -- they're simply traveling up and over, rather than just over. Unless I'm missing something here.
The number of things of a given size you can fit on a plane within distance R of you is proportional to R^2. The number of things you can fit in a three dimensional space is R^3. So as we utilize 3D more and more things will tend to be closer together.
They're closer together, but the distance traveled in total is the same. Imagine the transistors are pieces of paper, and you're drawing a line over them. If the paper is flat, then you're drawing a line of distance n, and the points are n apart. If you fold the ends of the paper together, then the points are 0 units apart (or near enough to make no matter), but that line still has a distance of n.
Oh, I think I get what your confusion is now. The signal doesn't have to travel up and over now any more than it did when everything was flat. The signal will travel up a few gate widths to the low resistance metal interconnect layers, travel a few tens or hundreds of gate widths sideways to get to the next transistor, then goes down again to make the connection. Going to 3D doesn't change this except to make the up and down slightly longer and sideways much shorter.
The previous commenter wasn't talking about this transistor 3d feature, but about stacked transistors. Just like a city full or high-rise buildings can pack a lot more people in per square mile, a stacked transistor IC could pack a lot more transistors per square mm.
He was just referring to packing more transistors in a given area. The theory is that the far transistors of SRAM cache are closer than they would be at a lower density, and that difference might make a performance difference.
I'm not sure what the electrical propagation speed is in modern ICs, but let's assume its about 1mm per pico-second (3 times that of vacuum). So for each mm we move our cache elements closer we gain 2 ps in round-trip delay. On a 3GHz processor you've got 333 ps per cycle, the i5 die is about 13mm across, going from 32 to 22nm process might shave as much as 3 or 4mm of the longest path. Giving a 6 to 8ps gain, potentially a 2% improvement. Interesting.
> let's assume it's about 1mm per pico-second (3 times that of vacuum).
If Intel had found a way of making signals propagate three times faster than the speed of light in vacuum, everyone would be too busy rewriting the laws of physics to take notice of their transistor technology improvements.
A 3mm path-length difference would be more like 10ps; 20ps for a 2x3mm round trip.
(But I bet Intel take a lot of trouble to reduce those distances. There probably isn't anything that has to happen in a single cycle that involves 6mm-worth of propagation delays.)
It is as you said - instead of the gate controlling the flow in a shallow ditch (the old "2D" does have some depth ;-), they built up a pipe and the gate is the choke around it.
Well, that should help stem the pesky leakage current problems that plague the deep sub-micron technologies ...
I'm a sucker for videos. This Tri-Gate tech was first announced in 2002, I love seeing pie in the sky technology come into reality and widespread usage.
From what I've heard, using 50% as much power for the same performance as the previous generation still will not be sufficient to bring Intel's Atom performance/energy consumption ratio to that offered by ARM chips. However, it's a huge leap in the right direction. Add better-designed power-saving features on the next generation of Atom chips, and future process shrinkages, and it's easy to see ARM's lead getting chipped away until it's gone.
This is orthogonal. An ARM Cortex (or GPU, or whatever) on this process would see similar gains.
It's also worth pointing out that current Atoms in the market are still 45nm parts, not even 32nm. Intel, for obvious reasons, tends to prioritize production of high-margin desktop and server CPUs over low-margin embedded parts.
Really, this announcement isn't about ARM-based vs. Intel-based SoC designs. I think it's clear that Intel has some catching up to do there. This is about Intel cementing and extending its complete and total dominance of high end digital logic fabrication. At this point they look to be about a full two years ahead of everyone else. AMD, IBM, Samsung, TI, TSMC and the rest of that crew have to be more than a little worried.
Objectivity disclaimer: my wife is at Intel working on precisely this 22nm process. So I'm about as biased a source as you can find.
> This is about Intel cementing and extending its complete and total dominance of high end digital logic fabrication.
Given that, (and given that Intel has been dominant in process technology for some time now) I've always wondered why Intel doesn't do fabrication for third party, high-performance/high-margin/high-power-budget products that don't directly compete with Intel's main CPU product line. Networking/telecom processors, top-end FPGAs, DSPs, and so forth. Is it just that they are at capacity making CPUs and don't see any need to get into that business? Or do they do it already and I'm just not aware?
I've worked with audio equipment that uses FPGAs, CPLDs, and DSPs for various purposes, and being stuck on relatively-ancient processes makes that equipment generate a lot more heat and fan noise than would be necessary with DSPs and FPGAs on a modern process.
Indeed. ARM chips are not better made, they are better designed- at least in regards to low power. It's an architectural thing. This is very much like the old software rule; a good algorithm on slow hardware will often outperform a bad algorithm on fast hardware.
> An ARM Cortex (or GPU, or whatever) on this process would see similar gains.
...provided Intel grants the IP, know-how and equipment to its rival.
> dominance of high end digital logic fabrication
Disruptions typically begin at the low-end, with the disrupted incumbent earning great margins at the high-end - just before they get killed. Smartphones are the low-end. ARM is probably already too well established there for Intel to win it (with popular machines, OSs and applications dependent on ARM).
The danger to Intel is that as ARM improves in performance, it brings other benefits with it (eg. low power consumption; configurability), that are also valuable in high-end logic. Once ARM is performant enough, those server-farms could switch, to solve their heating/power problems.
But it's interesting that Intel hasn't made the low-end a priority, not applying their best process to it; maybe they have a reason to think they're safe.
but surely it is patented to a crazy extent, and therefore we won't be seeing it hit ARM stuff unless Intel lets it? so I doubt we will see orthogonal gains immediately from it.
Saw a rumor recently that Apple would be getting Intel to fab ARMs for them. Seems unlikely, but could potentially give Apple a lead (for a while) in one more area of their vertical integration play.
Atom is 2 generations behind in the manufacturing process compared to this. They'll barely start making them at 32 nm next year, and that will last for another 2 years.
Intel recently announced that they're going to catch up Atom (semi-misleadingly marketed as "faster than Moore's Law") so they're at 45 nm now, they'll release 32 nm Atom later this year and 22 nm Atom in early 2012.
That's not what they meant. They meant that instead of doubling Atom in performance every 18-24 months(have they even done that so far?), they'll try to double it every 12 months, just like the ARM chips are currently doing.
They can't switch the manufacturing process every year.
Interesting that Intel is seeking to fabricate ARM chips for Apple. I presume that Intel is pitching their best lithography process tech, i.e. 22nm. If Intel wrests Apples ARM CPU fabrication business away from Samsung - who competes with Apple on smartphones - then Intel would become a world leader in ARM CPU fabrication and pay ARM plenty of licensing fees!
The risk would be once Intel is the world's source of ARM CPU's, suddenly ARM's biggest competitor has a chokehold on the market's access to their silicon.
It would basically come down to whether Intel chose to embrace ARM, or tried to use the new position to quietly strangle it.
A large number of foundries currently make ARM CPUs, and a number of companies make ARM CPUs for in-house manufacturing. Intel could not get an absolute monopoly but rather a technical superiority advantage such as it currently has over other x86 vendors.
It has been speculated in the financial press that Intel might try to offset its huge annual capital expenditures by offering as much as 20% of its fab capacity as foundry services.
Anyone know if the 3D structure is patented by Intel? If so, wouldn't this give Intel a monopoly on transistors given how much better this new design performs?
No this design was developed back when I was in college, the revolutionary change here is that Intel has a process to actually manufacture these things effectively and get decent yield. IBM had these things built in test cases back in 2007 but didn't have a manufacturing method.
Intel will likely not patent or reveal the manufacturing method thats how most semiconductor manufacturing technologies go. They tend to be trade secrets that are a combination of process and machinery which your competitors are unlikely to ever reproduce exactly, so no point in patenting it.
"An alternative to the standard methods of building planar MOSFETs has been proposed to help alleviate some of the physical barriers to scaling down existing designs. These proposals involve the construction of three dimensional MOSFETs either in the form of a dual-gate transistor (FinFET) or as a tri-gate transistor as a replacement for the conventional planar MOSFET."
Intel doesn't have a monopoly on the technique, just a big technological head start. From the Anandtech article on this:"Intel isn't expecting its competitors to move to a similar technology until 14nm."
I don't know if it's patented, but TSMC is apparently working on deploying the technology (according to the NYTimes article linked above). So, there are definitely people who think that Intel doesn't have a monopoly on the design.
Plus, there's far from a consensus that this is the best design out there. It hasn't been proven in mass production yet. STMicroelectronics, a massive player in microcontrollers (which often go into applications with even tougher power constraints than mobile phones), is pushing Silicon on Insulator pretty for their next generations.
I think this will mostly help increase the life expectancy of the Moore's Law by another 10 years or so. When we'll get to 11nm or whatever is the limit, we'll just start stacking layers of transistors on each other. That will only work until the chips become too thick, though.
I agree with what you said, but I'm sorry you misunderstood my point. The ITRS lithography roadmaps for years have assumed that lithography would advance at the rate of 36 months between nodes, e.g. between 45nm and 32nm. But in response to AMD competition in the previous decade, Intel introduced their "tick-tock" cycle in which Intel advances the lithography node every 24 months. Other CPU fabricators have been forced to keep up with Intel's pace, and as you point out they have been a process generation behind.
As a result, 10nm will be released in 2015, rather than 2020 as ITRS predicted in much earlier roadmaps.
What gets real interesting in just a few years is how Intel and others will get below 10nm. Could be a shift to carbon based structures will be necessary.
Well Intel was hoping to hit 10Ghz with the Pentium 4 & we know how that worked out. Perhaps they'll hit 10nm in 2015, but a "small delay" in new process technology usually seems to be "12+ months".
Curious as to what clock speeds will be available when Ivy Bridge is released in the first half of 2012? If one expects a 37% performance increase at low voltages, then what would be the performance increase at standard voltage? 20% or so?
Anantech gives a gate-delay chart and explains that Ivy Bridge will be 18% faster at the standard voltage compared to Sandy Bridge. That might mean Ivy Bridge CPU parts at 4 GHz as compared with Sandy Bridge parts at currently at 3.4 GHz.
Thats how transistors work in general, but the problem is you get small enough and its like the transistors want to turn them-selfs on, luckily the smaller you go the more leakage you get into other areas of the chip so those extra electrons just get seeped into there and ground out which mostly causes you to pull more power per square area.
You real issue is if those "jumping" electrons get wedged into corners near gates, then they can leave a transistor on permanently. But that's all part of the chip design process to avoid that kind of thing.
I predict that, two years from now, it will be mentioned 28 times. And so on, doubling every two years. I call this trend "Moore's Law," because all such trends are eventually mislabeled as Moore's Law.
Absolutely! IBM's was never motivated to improve performance for their mainframe and minicomputers as quickly as Intel improved performance for microprocessors.
Really, Moore's law is a sort of management principle rather than any kind of physical law. Simply, Intel introduces new fabrication process technology at the pace which optimises their profits.
Advance too slow and competitors will take the business, advance too fast and capital costs are higher, plus customers need payback on their current purchases. Advance at just the right pace and customers are motivated to replace perfectly good products just a few years old.
I don't mean to trivialize this, but "reinvent" sounds a little strong to me. This is a modification on silicon design, and a great one, but is just another notch in the miracle of Moore's law. It's more evolutionary than revolutionary.
Although not the link for this story, the fact that this story broke in the NYT (not that surprising), with an explanation to attempt transistor design and functionality (incredibly surprising) is really uplifting. A good piece of purely anecdotal evidence against those who claim America is in perpetual intellectual decline. The general populace IS interested enough to try to understand complex ideas.
Clock speed is just another metric, not the most important one. You also have chips that do several operations per clock cycle, low power consumption chips, chips that do parallel processing. All these factors affect performance as well.
I would argue that neither of those things are metrics to measure for a transistor, since they are affected by how its used. Properties of the transistor itself are what matter: size, drain and source capacitance, leakage current when off, drain-source voltage drop when on, and probably a dozen things I don't really know about.
The properties you mention are mainly "low level" properties, which in the end affect the "high level" properties that are speed and power consumption. For example capacitance limits clock speed and also has an effect on power consumption, and leakage current reduces power efficiency. Capacitance and leakage current themselves depend on size. I think that the physical properties you mention (and maybe others) may be used to create a model, which can then be used to estimate clock speed and power consumption at different operating points.
I would think that they are talking about clock frequency. They do say that you can either have the 37% performance increase, or use less than half the power when at the same performance.
It's probably easier to use that much less power for the same performance than to push the same power in and get higher performance. On smaller size scales power leakage and heat dissipation become bigger issues so you might not be able to push the same amount of energy through as with the larger scale chip.
"Performance" doesn't really mean anything by itself without more details in this context, its just a vauge marketing phrase. Go look at the switching-speed/voltage tradeoff charts that pilom linked to at Anandtech to get some meaningful but still very impressive information.
No, that limit has been hit by the physical structure of Silicon itself. The perf has to do with more transistors per square area, thus you could fit more "cores" into a single chip or for example, it takes me 2mil transistors to make a 5 clock cycle multiplier but I could get a 1 clock cycle multiplier if I used 5mil transistors. I didn't use to have the physical real estate to do it, now I would, so I'd do the same operation in 1/5 the time.
All of those papers either post-date Intel's announcement from 2003 regarding tri-gate transistors, or are written by Intel employees. That search also brings up multiple patents held by Intel on the technology.
There's an enormous difference between writing a paper on a design and prepping up to produce them at Intel's scale. Even if they didn't invent the object, they invented the processes to make it a reality outside of a lab.
It will be interesting to see whether patents will make this a defensible innovation. Will AMD et all have to invent a similar but materially different technology in order to keep pace?
Considering Intel first announced the Tri-Gate tech in 2002 AMD would have to had been working on something for 9 years to be launching a competitor anytime soon.
It's building electronic components vertically instead of laid out flat (think of a book stood on an edge rather than laid down, kind of). That has two advantages - they take up less room and they don't leak so much electricity to the silicon that they're sitting on.
The process causes the gate to be exposed to a larger surface area of the source, thus allowing it to have greater control. How? by going 3D. Why? Think of it as a heatsink. If your heatsink was just a flat surface, it would suck. But because it has fins (or pins, or whatever 3d shapes that come out of it), it has greater exposure to ambient air.
Apple obviously had a heads up on this - since they announced the switch to intel not long ago. Which means they had insider information. I wonder if anyone made billions off it.
As a consumer he might not have any good reason to do so, but look at it from Intel's perspective: They're potentially not getting the best return on their R&D investment by encouraging customers to regularly skip generations.
http://www.anandtech.com/show/4313/intel-announces-first-22n...