> Cache and out of order buffers (speculation) is what is behind latest security issues.
That's one way to look at it. Another is that opaque CPU designs are a big issue (at least for meltdown, which is a bug; spectre is more of a broken design philosophy).
Today there is a benefit from the higher code density of CISC. 1. Less memory bandwith expended moving instructuons into I-cache. 2. Less die area spent on I-cache per unit of "code functionality", however you mesure that.
RISC only made sense when logic cycle times, memory cycle times, and I/O cycle times were at rough parity.
If you read the rest of the thread, you'd find that both of your points are moot, as RISC-V code density is no worse than x86-64.
As for your claims on RISC not making sense, I'll just say it makes more sense than ever, as complexity leads to issues, which could affect security, and security is important in the present networked world.
Nowadays it just doesn't matter, because CPUs translate ISA into whatever they please.
Cache and out of order buffers (speculation) is what is behind latest security issues.